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Digital Down Conversion (DDC)


An interpolating filter chain, a numerically controlled oscillator (NCO), and a mixer comprise the Digital Up Conversion (DUC). The filter chain consists of a low-pass interpolator, a half-band interpolator, a CIC compensation interpolator (FIR), a CIC interpolator, and CIC gain correction.


The first low-pass interpolator achieves the precise Fpass and Fstop features of the DUC. A half-band filter is a form of the middle-of-the-road interpolator. Because sample rates are lower at the beginning of the chain, the earlier filters can maximize resource use by sharing multipliers. The CIC compensation interpolator improves the spectral response by accounting for later CIC droop when interpolating by two. The CIC interpolator has a high interpolation factor that is enough for filter chain upsampling.


The DUC’s input interpolation factor is 2 and a decimation factor of 256 to achieve an output sample rate of 270.83 kHz. For cell search and master information block (MIB) recovery, LTE receivers typically employ a sampling rate of 1.92 Msps. The Digital Upconverter filters are specifically built for this use. The DUC has been designed to operate at a clock rate of 122.88 MHz.


 Conversion Features and Process:


  • Complex mixer functions should keep 18 bits at the input and truncate to 16 bits at the output
  • Maintain 16 bits in/out of DDC
  • The frequency error is calculated during the synchronization process and added before demodulating the Rx packet
  • Frequency error term = 0 for Tx slots
  • The output frequency is the sum of a constant frequency term, a tune frequency term, and an error frequency term
  • DDC shares a single DDS FPGA instantiation
  • DDC shares the same FPGA filter structures
  • DDC is implemented using Xilinx ip with Taylor series phase correction
  • Reference Frequency = +/- 1 ppm
  • Max Doppler Velocity = 700 m/s