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Physical Design Engineer

Physical Design Engineer

Posted time 2023/12/20

Faststream is hiring a Seasoned Physical Design Engineer for our ASIC/SoC/IP Core endeavors. Here are some details on what is expected.

 

  • Lead all block/chip-level PD activities.
  • Assist with PD activities including floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification.
  • Work in collaboration with the design team for addressing design challenges.
  • Help team members in debugging tool/design-related issues.
  • Look for improvement in RTL2GDS flow to improve PPA.
  • Troubleshoot a wide variety up to and including difficult design issues and applied proactive intervention.
  • Be responsible for all aspects of physical design and implementation of ASICs/SoCs/IP Cores targeted towards 5G, IoT, Networking, Wireless Charging markets.

 

Requirements:

 

  • BE/B.Tech/M.Tech, or equivalent experience.
  • 5+ years of experience in Physical Design.
  • Strong understanding of the RTL2GDSII flow or design implementation in leading process technologies.
  • Proven experience of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
  • Expertise in high-frequency design methodologies.
  • Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus, etc used in the RTL2GDSII implementation.
  • Strong knowledge and experience in the standard place and route flow ICC2/Synopsys and Innovus/Cadence flow preferred. Well-versed with timing constraints, STA, and timing closure.
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry-leading Place & Route tools.
  • Ability to multi-task and flexibility to work in the global environment.
  • Good communication skills and strong motivation, Strong analytical & Problem-solving skills.
  • Proficiency using Perl, Tcl, and Make scripting is preferred.

    • Faststream is hiring a Seasoned Physical Design Engineer for our ASIC/SoC/IP Core endeavors. Here are some details on what is expected.

     

    • Lead all block/chip-level PD activities.
    • Assist with PD activities including floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification.
    • Work in collaboration with the design team for addressing design challenges.
    • Help team members in debugging tool/design-related issues.
    • Look for improvement in RTL2GDS flow to improve PPA.
    • Troubleshoot a wide variety up to and including difficult design issues and applied proactive intervention.
    • Be responsible for all aspects of physical design and implementation of ASICs/SoCs/IP Cores targeted towards 5G, IoT, Networking, Wireless Charging markets.

     

    Requirements:

     

  • BE/B.Tech/M.Tech, or equivalent experience.
  • 5+ years of experience in Physical Design.
  • Strong understanding of the RTL2GDSII flow or design implementation in leading process technologies.
  • Proven experience of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
  • Expertise in high-frequency design methodologies.
  • Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus, etc used in the RTL2GDSII implementation.
  • Strong knowledge and experience in the standard place and route flow ICC2/Synopsys and Innovus/Cadence flow preferred. Well-versed with timing constraints, STA, and timing closure.
  • Good automation skills in PERL, TCL, tool specific scripting on one of the industry-leading Place & Route tools.
  • Ability to multi-task and flexibility to work in the global environment.
  • Good communication skills and strong motivation, Strong analytical & Problem-solving skills.
  • Proficiency using Perl, Tcl, and Make scripting is preferred.