DFT Engineer | Faststream Technologies

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Location Bangalore Job type Full Time
Posted time 2022/05/18 Location Bangalore Job type Full Time

 

Job description

    • Implementation and Integration. Hands-on experience and knowledge of ATPG, ATPG-DRC clean-up, Pattern Generation, fault models, coverage analysis, and improvement.
    • Hands-on experience with pattern generation for various fault models, Stuck-At, TDF, PDF, IDDQ.
    • Experience with pattern verification, simulation debug, ATE pattern delivery, and silicon bring-up.
    • Experience with one or more scan/ATPG solutions with Tessent Scan, Fast Scan, Test Kompress
      Synopsys DC, DFTC, DFTMAX, Tetramax.
    • Experience with pattern verification and debug VCS, Simvision, NC-Verilog, Questa.
    • Desired experience with failure diagnostics, silicon debug, and interfacing with ATE and test engineers for bring-up.
    • Preferred but not required MBIST implementation and experience with MBIST pattern generation and verification.
    • Preferred but not required experience with one or more MBIST solutions Tessent BIST, MBIST Architect, SMS
    • Experience with shell scripting, Verilog, Tcl, and/or Perl/Python
    • Strongly desired to understand IEEE 1149.1, P1500, and Core-Based Testing Standards
    • Desired experience with coverage improvement and yield improvement
    • Desired experience with test constraint generation and working with STA for test mode timing closures

 

Experience

    • Minimum 4 years of experience in areas of SOC-DFT

 

Job description

    • Implementation and Integration. Hands-on experience and knowledge of ATPG, ATPG-DRC clean-up, Pattern Generation, fault models, coverage analysis, and improvement.
    • Hands-on experience with pattern generation for various fault models, Stuck-At, TDF, PDF, IDDQ.
    • Experience with pattern verification, simulation debug, ATE pattern delivery, and silicon bring-up.
    • Experience with one or more scan/ATPG solutions with Tessent Scan, Fast Scan, Test Kompress
      Synopsys DC, DFTC, DFTMAX, Tetramax.
    • Experience with pattern verification and debug VCS, Simvision, NC-Verilog, Questa.
    • Desired experience with failure diagnostics, silicon debug, and interfacing with ATE and test engineers for bring-up.
    • Preferred but not required MBIST implementation and experience with MBIST pattern generation and verification.
    • Preferred but not required experience with one or more MBIST solutions Tessent BIST, MBIST Architect, SMS
    • Experience with shell scripting, Verilog, Tcl, and/or Perl/Python
    • Strongly desired to understand IEEE 1149.1, P1500, and Core-Based Testing Standards
    • Desired experience with coverage improvement and yield improvement
    • Desired experience with test constraint generation and working with STA for test mode timing closures

 

Experience

    • Minimum 4 years of experience in areas of SOC-DFT