AUTOMOTIVE INFOTAINMENT MULTIMEDIA SoC 

We defined the verification methodology, designed the verification platform (test bench), and verified important modules for a complex 32-bit Automotive-grade SoC with multimedia/connectivity features.

• Defining the methodology for verifying the SoC with HDL, VERA, and UVC based models for the various macrocells of the SoC.
• Creating the Test bench for carrying out the SoC level verification activities.
• Verifying modules like the System Clock Controller, USB OTG, Ethernet, ARM’s TCM implementation, and remap features.
• Generating the RTL for USB OTG and USB HOST with the required configuration. Designing the USB Sub-System and integrating the same to the SoC’s AMBA backbone and pads.
• Supporting the above-mentioned IP’s right through silicon validation.
  • Tools used:-
    • Platform:  Solaris and Linux LSFs
    • Languages: Verilog
    • Digital Simulator: NCSI
    • Models: Synopsys VERA models (VIP).
    • IP’s used: Designware USB OTG and USB HOST IP from Synopsys