June 13, 2024 
India, USA 
Remote 
Qualifications
3 years of experience in characterizing standard-cells.
Experience in writing spice decks and basics of CMOS circuits.
Master’s degree in VLSI Integration, Computer Engineering, Electronics Engineering.
Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido.
Experience with characterization tools (e.g., SiliconSmart, Liberate).
Experience in PERL/Shell/TCL scripting or similar languages, with the ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages.
Understanding of CMOS circuits and timing concepts (e.g., setup, hold).
Understanding of Liberty Variation Format (LVF) and Composite Current Source (CCS) models.
Responsibilities
Perform statistical simulations to ensure the robustness of custom circuits.
Participate in Silicon-Spice correlation activities to improve Performance, Power, Area (PPA) of custom digital circuits.
Collaborate closely with the internal circuit design team and the System-on-a-Chip (SoC) team and understand customization requirements.
Design and implementation of the combinatorial, clock, power management, and sequential circuits.
Parasitic extraction and circuit optimization for power/performance/robustness/density.
Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models).
Physical View (NDM, LEF, GDS, OASIS, OALIBS) generation for standard cell libraries.
Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. APL characterization and modeling.
Developing functional models behavioral Verilog, power up Verilog and fault models.
Development of automation for library modeling, validation, quality checking, performance, and reliability verification.
The library build, validation, QA, release, and support.
Technically lead, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies
Qualifications
3 years of experience in characterizing standard-cells.
Experience in writing spice decks and basics of CMOS circuits.
Master’s degree in VLSI Integration, Computer Engineering, Electronics Engineering.
Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido.
Experience with characterization tools (e.g., SiliconSmart, Liberate).
Experience in PERL/Shell/TCL scripting or similar languages, with the ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages.
Understanding of CMOS circuits and timing concepts (e.g., setup, hold).
Understanding of Liberty Variation Format (LVF) and Composite Current Source (CCS) models.
Responsibilities
Perform statistical simulations to ensure the robustness of custom circuits.
Participate in Silicon-Spice correlation activities to improve Performance, Power, Area (PPA) of custom digital circuits.
Collaborate closely with the internal circuit design team and the System-on-a-Chip (SoC) team and understand customization requirements.
Design and implementation of the combinatorial, clock, power management, and sequential circuits.
Parasitic extraction and circuit optimization for power/performance/robustness/density.
Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models).
Physical View (NDM, LEF, GDS, OASIS, OALIBS) generation for standard cell libraries.
Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. APL characterization and modeling.
Developing functional models behavioral Verilog, power up Verilog and fault models.
Development of automation for library modeling, validation, quality checking, performance, and reliability verification.
The library build, validation, QA, release, and support.
Technically lead, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologies