Senior Design Verification Engineer FPGA/ASIC

Job description

• • Strong in UVM/System Verilog/C/C /scripting, Simulation, Formal verification, Emulation, post Silicon validation.
  • Knowledge of system-level architecture including buses like AXI4/AXI5/AHB is a must.
  • CHI knowledge is an advantage.
  • Knowledge of CMN (Coherent Mesh network) is an advantage.
  • Excellent waveform debug skills using front-end industry-standard design tools like VCS, NCSIM, Verdi, Model Sim.
  • Demonstrate the ability to work with cross-functional teams.
  • Familiarity with processors and boot flow would be useful.
  • Familiarity with Software development flow including assembly and C is beneficial.
  • Requires a strong understanding of the state of the art of verification techniques, including assertion and metric-driven verification.
  • Experience in full chip verification is a plus.
  • Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Identify and write coverage measures for stimulus quality measurements.
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics.

• Responsibilities

  • B. Tech / M. Tech degree in Electrical/ Electronics/ Computer science.
  • Knowledge of Assertion based formal verification, Analog AMSD Cosim will be a plus
  • Exposure to industry-standard verification tools is required
  • Good Knowledge in Processor/SoC architecture, DSP fundamentals.
  • Good verbal and written communication skills to work effectively with teams spread geographically.
  • Good debugging and analytical skills.

• Experience

  • 3-8 years of experience in design verification with UVM and constrained random coverage-based verification approaches.

   

Apply Now