Physical Design Engineer (4+ Years) – Bangalore

Job Description

• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floorplanning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
• The role involves analyzing DRC, LVS, ERC rule files for industry-standard layout verification.
• Multiple Power Domain Analysis using standard Power Formats UPF/CPF

Skills Required

• Experience in ASIC Physical Design RTL to GDSII Implementation flow.
• Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc.
• Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal)
• Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM etc.)
• Physical Verification (DRC/LVS/Density/Antenna etc.)
• Reliability Verification (EM/IR drop etc.)
• Well versed with TCL/Perl/Shell Scripting
• EDA tool knowledge: Design Compiler, ICC/ICC2, Spectre, Virtuoso, Primetime, ICV

Qualifications

• BE/B.Tech/M.Tech in Electronics and Communication Engineering/VLSI Design

Experience

• 4+ Years in Physical Design