TOP-LEVELVERIFICATION APPROACH

Verification is always a major challenge in your project, ensuring that your design is bug-free within the given time constraints. With ever-increasing size of ASIC and FPGA, the complexity of verification is increasing exponentially. Each small change in configuration is bringing about long verification. Subsequently, 50-70% of chip development resources are currently getting devoured by verification efforts. With processor now part of SoC, the complexity of verification further increases.Our team has broad involvement in taking up full responsibility or being part of larger customer team, delivering module to full-chip verification for complex chips. We have worked with simple verification environment created using simple Verilog or VHDL to full coverage driven random environment in System Verilog using UVM. Our team has developed reusable Verification components without any preparation and also utilized industry standard VIPs as a major aspect of condition to lessen the time and enhance nature of check. We have verified various chips, pre, and post-silicon, to ensure highest quality working chips.

Advanced ASIC Verification:

We provide an exhaustive scope of ASIC verification services to help our clients to accomplish working silicon first time around. Verification represents one of the biggest challenges confronting IC developers getting their design into the market inside acceptable timescales. Silicon technology continues to advance giving increasing scope to incorporate an extensive variety of IP including digital/analog cells, embedded processors, memories, high-speed IO, in-house/3rd party IP and so on onto a single device. Traditional verification techniques (e.g. directed testing) basically can’t adapt to this complexity. We comprehend the difficulties introduced by these designs and work with our customers to give everything from in-depth knowledge to solve a specific verification problem, to delivering a comprehensive verification solution for a complete chip.

 

Digital ASIC/SoC Design and Verification:

Our design and verification offerings under the digital ASIC/SoC Design and verification portfolio envelopes:

  • Synthesizable IPs (RTL) for digital functional blocks including high-speed DSP functional block sets
  • Synthesizable IO protocols
  • Memory and Microcontroller Interface Protocols
  • High-Speed Arithmetic Functions
  • Verification IPs for an assortment of functional blocks and IPs
  • Design support for Physical Design and Verification
  • Complete Chip Integration