Verification is always a major challenge in your project, ensuring that your design is bug-free within the given time constraints. With ever-increasing size of ASIC and FPGA, the complexity of verification is increasing exponentially. Each small change in configuration is bringing about long verification. Subsequently, 50-70% of chip development resources are currently getting devoured by verification efforts. With processor now part of SoC, the complexity of verification further increases.Our team has broad involvement in taking up full responsibility or being part of larger customer team, delivering module to full-chip verification for complex chips. We have worked with simple verification environment created using simple Verilog or VHDL to full coverage driven random environment in System Verilog using UVM. Our team has developed reusable Verification components without any preparation and also utilized industry standard VIPs as a major aspect of condition to lessen the time and enhance nature of check. We have verified various chips, pre, and post-silicon, to ensure highest quality working chips.