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Verification IP

USB 2.0 SystemVerilog
Verification IP

Faststream Technologies USB 2.0 SVC can be configured as USB host, compound device or monitor. It provides protocol checking, transaction-level monitoring, and coverage. It can be used for verification of host or device IP.

 

Features:

 

  • Supports following error injection : Sync Field pattern error, False EOP error, Omit EOP error, Bit stuff error, CRC5 error, CRC16 error, Inverse PID error, a Byte boundary error, Payload size error, No response to transactions, Token error
  • Supports protocol checking including error detection of CRC, SYNC field, EOP, Bit stuffing, PID
  • Supports Transaction recording using the scoreboard
  • Supports Transaction Coverage
  • Supports reset signaling
  • Supports Suspend/Resume signaling
  • Auto-detection of device connect/disconnect
  • Configurable Timing parameters for reset, suspend, resume signaling

Block diagram:

 

 

SystemVerilog