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Verification IP

UART VIP

UART Verification IP provides a smart way to verify the UART component of a SOC or an ASIC. The Faststream’s UART Verification IP is fully compliant with standard UART 16550.UART VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is a GUI based debugger to speed up debugging.

 

Features:

 

  • Fully compatible with 16550.
  • Transmit and receive commands allow the user to transmit and receive UART data.
  • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
  • Configurable baud rate.
  • Full duplex operation.
  • Fully configurable serial interface.
  • Supports character width from 1 bit to 32 bits.
  • Supports number of stop bit configuration.
  • Supports different types of parity insertion
  • Even parity
  • Odd parity
  • Space parity
  • Mark parity
  • No parity
  • Error injection capability
  • Parity error
  • Framing error
  • Configurable receive FIFO depth.
  • Supports constraints Randomization.
  • Callbacks in transmitter, receiver and monitor for user processing of data.
  • On-the-fly protocol and data checking.
  • Auto CTS/auto RTS hardware flow control.
  • GPIO are supported using read and write commands.
  • Supports IRDA protocol.
  • Ability to transmit strings to help verification of SOC.
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
  • UART Verification IP comes with complete test suite to verify each and every feature of UART specification.
  • Status counters for various events in bus.
  • Functional coverage for complete 16550 features.
  • Supports 16 General purpose output and input pins.
  • Monitor detects following
  • Parity errors
  • Framing error

Benefits:

 

  • Faster testbench development and more complete verification of UART designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Deliverables:

 

 

  • Complete regression suite containing all the UART test cases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task, and functions used in verification env.
  • The documentation contains User’s Guide and Release notes

 

Block diagram:

 

 

UART