Get in Toucharrow


IP Cores

Verification IP

Synthesizable MIPI I3C Bus

Functional Model

Faststream Technologies synthesizable I3C model is a configurable, fully functional model compliant to the MIPI I3C specification that can be targeted to a range of emulation systems. The synthesizable I3C model enables the user to extensively debug their device in simulation and then conduct intensive validation in FPGA or emulation systems.




  • Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
  • Fully synthesizable SystemVerilog/Verilog RTL
  • Backdoor interface for control, monitoring and data exchange (with internal FIFO)
  • Support for both I3C master and slave roles
  • Master device roles include I3C Main Master, SDR-Only Main Master, I3C Secondary Master and SDR-Only Secondary Master
  • Slave device roles include I3C Slave and I2C Slave (with or without 50ns spike filter)
  • Support all three HDR modes (HDR-DDR, HDR-TSP and HDR-TSL)
  • Full Common Command Codes (CCC) command interpreter
  • Hot-Join mechanism support
  • In-Band Interrupt (IBI) support
  • Support of all the standardized SDR error detection types (S0-S6, M0-M2) plus additional HDR errors (parity, framing, symbol and CRC5)
  • Controlled error injection on both SDR and HDR modes
  • Checks can be enabled or disabled individually or by group
  • Error flag/status for simple error monitoring
  • Targeted for simulation platforms (Cadence Incisive, Synopsys VCS)
  • Targeted for FPGA based systems (Xilinx/Altera) and ARM integrator
  • Targeted for emulation systems (Cadence Palladium, Cadence Protium, Synopsys Zebu, Synopsys HAPS, Mentor V-Station)




  • Full Verilog RTL available
  • Fully functional model for simulation emulation and FPGA environments
  • Highly configurable
  • Easy to use (comprehensive user guide)
  • Wide range of protocol and timing checks
  • Flexible implementation of the upper level communication layers by software



  • les
  • Full RTL synthesizable code that can be used by one Customer in any number of projects.
  • Full documentation for the product
  • Synthesizable sanity testbench
  • Enabling the user to check the correct instantiation & configuration of the BFM without using a debugger
  • Full support based on yearly maintenance
  • Also available on request:
  • Full verification environment for BFMs coded in SystemVerilog using UVM methodology and full Verification specification
  • I3C Synchronous/Asynchronous Time Control support

Block diagram: