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Verification IP

PCIe Gen 3
Verification IP

Faststream Technologies PCIe Gen3 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen3 interface of an IP or SoC.

Faststream’s PCIe Gen3 VIP is fully compliant with standard PCI Express® Base Specification Revision 3.0. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.

 

Features:

 

  • Compliant with PCI Express Specifications 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
  • Verification IP configurable as PCI Express Root Complex and Device Endpoint.
  • Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
  • Supports PIPE with configurable pipe width 8, 16, 32 with backward
  • compatibility.
  • Support link width, data rate negotiation and lane to lane deskew.
  • Support split a port to more than one link ‐ multi link.
  • Supports Low Power management LTSSM states ‐ L0s, L1, L2, PCI‐ PM, ASPM.
  • User Configurable fields ‐SKP interval count, FTS transmission count.
  • Support for on the fly change in link speed and linkwidth through single test.
  • Single Virtual Channel (VC) and Multiple VCs Endpoint.
  • Configurable number of functions.
  • Supports 128B, 256B, 512B, 1kB, 2KB or 4kB Maximum Payload Size (MPS).
  • Interrupt support: INTx or MSI MSI‐X and ECAM support.
  • Advanced Error Reporting (AER) with optional Malformed TLP checks, ECRC and TLP Poisoning support.
  • Support for the whole compliance ‐TL, DL, PL, Configuration and power management Test Plan and Test Sets.
  • On the fly protocol checking using protocol check functions, static and
  • dynamic assertion.
  • Built-in Coverage analysis.
  • Provides a comprehensive user API (callbacks).
  • Graphical analyser for all three Layers to show PCIe transactions for easy debugging.

Benefits:

 

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover
  • points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.

 

Deliverables:

 

  • PCIe Gen3 Root Complex/Device_endpoint
  • PCIe Gen3 BFM/Agents for :
  • PHY Layer
  • Data Link Layer
  • Transaction Layer
  • PCIe Gen3 Layered Monitor and Scoreboard
  • Test Environment & Test Suite :
  • Basic and Directed Protocol Tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
  • Compliance Tests
  • Integration Guide, User Manual, and Release Notes

Block diagram:

 

 

PCIE-GEN-3