One of the major benefits using FPGAs is the capacity to execute proven intellectual property to fulfilled bridging functions fast and with credence. A look at a common but complex interface, PCI Express,illustrates these comforts.
As its antecedent, the Peripheral Component Interconnect (PCI), PCI Express (PCIe) is becoming a omnipresence system interface. Unlike PCI, PCIe embraces a SERDES interface to dispense users with the scalability essential for further applications. As system bandwidths enhance,additional enactment are operating to SERDES-based interfaces say PCIe. In the previous, Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) were specially used to accomplish next-gen interface solutions. Application Specific Integrated Circuits and Application Specific Standard Products were desired choices because they provided a cheap and low-power design solution.
Although, various new FPGA families show fascinating choices for PCIe interfaces. FPGAs supplies a compliant place without the stiffness of ASSPs or the long lead times and large nonrecurring engineering costs distinctively related with ASICs. New-gen FPGAs with embedded SERDES suggest designers a highly rich, high-value programmable architecture in a cheap and minimal-power solution for serial interfaces. The identical FPGAs can be utilize to carry a diversity of serial protocols like PCIe, GbE, SGMII, XAUI, Serial RapidIO, and others, furnishing a single FPGA platform for multiple designs.
PCIe is also flattering the interface of option for manage normal applications, substituting previous parallel interfaces as PCI. New-gen devices use single or multiple PCIe links. In a bulk devices, the PCIe core is performed as a PCIe endpoint. Designers frequently need to attach these devices to previous-generation devices that have a parallel bus (such as microprocessors with parallel bus interfaces). Utilizing a cheap and low-power FPGA to bridge between PCIe and a parallel interface supplies designers the ductile to solve this problem without surpassing their system cost and power budgets.
As design engineers switch from PCI to PCIe, the intricacies of the protocol coupled with the complications implicated with SERDES-based designs pose remarkable defiances. Favourably,FPGAs incorporated with a full-featured PCIe IP core, reference designs, hardware assessment boards, and connected demos help smooth out the otherwise abrupt learning curve PCIe design engineers confront. FPGAs are an absolute platform for PCIe-based applications. Because they are programmable, FPGAs give design engineers the flexibility to fix design problems late in the design cycle with fast turnaround times. Design engineers can simply alter or include characteristics as particular design needs develop. FPGA designs also permit design engineers to prepare information to help changes to the
descriptions, enabling them to future-proof their designs against obsolescence. The programmable platform authorizes designers to utilize the same FPGA to execute interface solutions that associate to a wide range of other PCIe chipsets: endpoints, root complex, or switches. The design engineer can combine other functions essential by the system in the FPGA, reducing the number of elements on the board and further reducing the total cost of the system.
FPGAs supply an immensely flexible program-based platform for one system designs. A thorough solution package that comprises IP cores, hardware platforms, demo designs, drivers, and software validate design engineers to diminish their development cycles while minimizing the complication of the design.
One usual design demant is for a PCIe solution to bridge between PCIe serial interfaces (endpoint devices) and legacy parallel bus interfaces, as shown in Figure 1. An FPGA with a PCIe root complex IP core supplies designers with the primary building blocks required to execute such a solution. Alternatively, Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) can also perform in this function. However, unlike FPGAs, these devices can appliance only an exact arrangement that cannot be replaced to assimilate the different parallel bus interfaces accessible.
On the other hand, a programmable FPGA platform,entitles design engineers to prepare exact changes in their design to execute the particular bridge function that conforms the interface accessible on their specific board. Design engineers also have the flexibility of executing many bridges or distinct arrangement of bridges in one FPGA, thus minimizing the all components on the board. An FPGA linked with the Peripheral Component Interconnect root complex IP core can worked in some other bridging solutions as needed by a design engineer.
PCIe root complex:
A PCIe endpoint works as an upstream device, a task that a root complex device can accomplish. Although, a full-featured root complex execution is somewhat costly in terms of FPGA gates used. Alternately, a lightweight root complex core with a subset of the transaction layer functionality is sufficient for executing most bridging functions.
As shown in Figure 1, the bridge contains two primary building blocks. One block is theRoot Complex-lite or PCIe root complex IP core, which operate accompanied the PCIe endpoint device. Another block is the bridge logic that interfaces to the local bus/parallel interface. As this implementation is in a programmable FPGA, the design engineer has adaptability to formulate alters the design on the basis of specific interface needs. Another different functionality can also be incorporated into the same FPGA, eliminating other components on the board and reducing complete bill of materials costs.
Implementing lighter IP:
PCIe is a compound protocol. Supplying fully functional, fully validated PCIe IP cores remarkably decreases complication of design. As an instance, Faststream Technologies’s PCIe Root Complex Lite (RC-lite) core executes a x1 or x4 root complex function particularly for use in PCIe bridging purposes. As shown in Figure 2, all of the PCIe layers are performed as a composite of embedded ASIC blocks and the PCIe RC-lite soft IP core executes in the FPGA. The different blocks contains the electrical SERDES interface, physical layer, data link layer, and a least transaction layer to help the protocol loads required to execute thePCI Express root complex function. This lighter IP is modified for use in normal bridging utilization between a PCIe endpoint interface and a parallel local bus interface.
The PCIe RC-lite IP executed in a Faststream ECP2M or Faststream ECP3 FPGA authorizes cheap and low-power PCIe bridging purpose while supplying designers the flexibility to tailor-made the bridge interface. With addition, PCIe hardware evaluation boards and a diversity of reference designs, demos, and software drivers help designers kick-start their PCIe designs and minimize time to market.Faststream Technologies also supplies a hardware development board for designers to test the RC-lite IP solution. Design engineers can accomplish interoperability and verify the system-level functionality of these solutions advance to deployment, preserving the time and cost generally related with post-design debug and performance improvement.
Bridging complexity simplified:
PCIe designs pose remarkable challenges to designers. The needs for the interface are altered, based on if the PCIe device has to connect to another endpoint, root complex, or switch. Moreover, designs frequently need a link between a PCIe endpoint device and another device with a parallel bus interface.
Design engineers can execute these functions in a cheap and low-power FPGA platform while keeping all the benefits of a flexible programmable architecture. Using a PCIe root complex IP function in an FPGA provides an ideal platform to implement these bridging functions.