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Multi-Protocol 12.5 G Universal SerDes IP

Faststream Technologies 4-lane 12.5Gbps Universal SERDES macro includes all high-speed analog functions for high-speed data transport between chips over FR4 and similar PCBs and over high quality cables. It is optimized for low power operation and is suitable for a variety of communication protocols. 8b, 10b, 16b, 20b, 32b, and 40b input datapaths simplify design of link layers created from RTL using regular Standard cells and regular synthesis, place, and route flows. Supply noise immunity in the TX PLL makes the SERDES ideal for use in noisy mixed signal SoC environments.





  • 12.5Gbps universal SERDES IP
  • Support full, 1/2, 1/4 and 1/8 data rate mode
  • Support up to 12 TX/RX data lanes with shared PMU
  • Fractional PLL for wide data rate range selection
  • 32bit/40bit selectable parallel data bus
  • Independent channel power down control
  • Programmable transmit amplitude
  • Three taps configurable FFE up to 10dB boost
  • Embedded adaptive receiver linear equalizer
  • Perspective DFE module in the receiver
  • Build-in self-test with PRBS and user pattern generation and checking
  • Integrated on-die termination
  • Support receiver detection
  • Support OOB signal generation and detection
  • Support 5000ppm Spread Spectrum Clock generation and receiving
  • Flexible reference clock frequency range, both single-end and differential
  • Do not need any external component
  • Eye monitoring facility available
  • FCBGA Package support
  • ESD: HBM/MM >2000V/200V




  • CDL Netlist
  • Rich Verilog Model with Jitter and loop dynamics
  • Verilog testbench incorporating BIST
  • Liberty timing models (.lib)
  • IBIS AMI models on request
  • LEF layout abstract
  • RTL wrapper for interface to the controller including adaptive DFE; Optional Andes RISC and PIPE4.3 PCS
  • Comprehensive Application Note
  • Industry-leading support by IP designers
  • Support for package design, Signal Integrity modeling, and production test development.





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