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Verification IP

LPDDR4 Verification IP

Faststream Technologies LPDDR4 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR4 interface of an ASIC/FPGA or SoC.Our LPDDR4 VIP is fully compliant with Standard LPDDR4 Version JESD209-4 specifications from JEDEC. This VIP is a lightweight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.




  • Supports LPDDR4 memory devices from all leading vendors.
  • Compliant to JEDEC LPDDR3 Specification version JESD209-4.
  • Supports multiple densities: 4Gb to 32Gb
  • Supports capturing of all the valid LPDDR4 commands as per the specs.
  • Supports dual channels which can function independently
  • Supports Data Bus Inversion
  • Constantly monitors LPDDR4 behavior during simulation.
  • On-the-fly protocol and data checking.
  • Supports Programmable READ/WRITE Latency timings.
  • Support for All Mode registers programming.
  • Support CA training and DQ calibration.
  • Support write data mask and data strobe features.
  • Support for Power Down features.
  • Support for full-timing as well as behavioral versions in one model.
  • Support for all timing delay ranges in one model: min, typical and max.
  • Built in functional coverage analysis.
  • Reports various timing error signals, which can be used to check for any timing errors
  • Provides full control to the user to enable / disable various types of messages
  • Integrates easily in any verification environment
  • Supports full timing models or bus functional models
  • Supports advanced SystemVerilog features like constrained random testing
  • Supports Callback / User Configuration in Monitor, Controller and Memory Model BFMs Supports wide variety of Dynamic as well as Static Error Injection scenarios
  • On the fly protocol checking using protocol check functions, static and
  • dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller
  • and Memory Model BFMs.
  • Graphical analyser to show transactions for easy debugging.



  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP
  • and SoC environment



  • LPDDR4-SDRAM Model
  • LPDDR4 Monitor and Scoreboard
  • LPDDR4 Memory Controller BFM/Agent
  • Test-Bench Configurations
  • Test Suite (Available in Source code) :
  • Basic Protocol Tests
  • Directed & Random Tests
  • Assertion and Cover Point Tests
  • Integration Guide, User Manual and Release Note

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