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Verification IP

LPDDR4 DRAM Memory Model

LPDDR4 DRAM Memory Model is implemented as per JEDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system. It is a part of Faststream’s comprehensive low power verification suite which also includes LPDDR4 DRAM DFI Functional Model and LPDDR4 DRAM Bus Monitor.




  • Supports multiple device densities: 4Gb to 32Gb
  • Supports capturing of all the valid LPDDR4 commands as per the JESD209-4A specifications
  • Supports programmable READ/WRITE latency and related timings
  • Supports all Power-Down modes
  • Support for Data Bus Inversion (DBI) RD/WR and Data Mask (DM) WR
  • Supports Mode Register (MR) programming
  • Multiple channel support that can function independently
  • Support callback for all Mode Register read/write, memory read/write which generates any scenario for verification and custom use
  • Reports all timing violations and protocol rule checks
  • Supports Target Row Refresh (TRR) and Post Package Repair (PPR)
  • Clock Stop and Dynamic frequency change to any valid DDR operating frequency




  • Developed using SystemC to facilitate seamless integration in any verification environment
  • Provides per channel transaction tracker to facilitate faster debug
  • Readily available for usage to software developers
  • Runs in every major simulation environment
  • Flexible licensing models
  • Customization and Integration services





  • Encrypted or Unencrypted SystemC Source code
  • Sample Scoreboard and Sanity test
  • UserGuide and Release notes
  • Examples’ showing how to connect and usage of Model

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