Get in Toucharrow

CONTACT US

IP Cores

Verification IP

LPDDR 4 / 3 PHY IP

Faststream Technologies Mixed-Signal LPDDR 3/4 PHY provides a turnkey physical interface solution for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed (up to 2133Mbps for DDR3 & LPDDR3, up to 2800Mbps for DDR4 & LPDDR4) applications with robust timing and a small silicon area. It supports all JEDEC DDR & LPDDR3/4 SDRAM components in the market. The PHY components contain DDR specialized functional and utility SSTL I/O’s, a critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

 

Features

 

  • DDR3-LPDDR3 and DDR4-LPDDR4 modes up to 2133Mbps, and 2800Mbps, respectively
  • x16/x32 data path interface extendable
  • JEDEC 1.2V SSTL I/Os and 1.1V LVSTL I/Os
  • Multiple drive strengths adjustable
  • Independent read and write timing adjustments with auto calibration
  • Low latency with programmable timings for secure data handling
  • Per bit de-skew support
  • Supports point to point memory sub systems and multi-rank
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power including self-refresh support
  • Low jitter with superior noise rejection
  • APB Port register access interface
  • Dual Row IO implementation and more
  • Implemented using 0.8V RVT&LVT core devices and 1.8V gate oxide IO devices
  • Supports both wire-bond and flip- chip packaging
  • Built-in ESD
  • Maintains self-refresh I/O drive state during VDD power down
  • DFI 2.1/3.1 compliant memory controller interface
  • Integral DFT

Benefits

 

  • Fully pre-assemble design, Drop-in hard macro to ease integration.
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • DFI2.1/3.1 compliant memory controller interface
  • Flexible pad ring configuration to adapt for various design and chip scenar.
  • Integration with other Faststream interface IP
  • Takes full advantage of process power savings and speed capability

 

 

Block diagram:

 

LPDDR-4