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Verification IP

Verification IP

Interlaken-FEC Verification IP provides a smart and effective way to verify Interlaken Features with 56G Speed features.The Verification IP is fully compliant with the latest Interlaken-FEC specifications and provides the following features.The VIP is compatible with UVM 1.x and upper methodologies and provides an extensive SV based coverage and assertions.




  • VIP support and configuration
  • IEEE 802.3bj clause91 (RS-encoder/RSdecoder).
  • Configurable SERDES bus width
  • Protocol checker
  • Coverage
  • VIP controls
  • Transcode Error insertion
  • Parameterized AM values
  • Parameterized AM repetition
  • FEC error insertion (Controlled and Random)
  • Skew insertion
  • Configurable SERDES bus width.
  • Gearbox width 32,40,64 & 80bits
  • Methodology & Support
  • Fully compliant to UVM
  • Call back support
  • Error insertion functions
  • Easy portable to all SV and UVM
  • Verification Environment



  • Faster test bench development and more complete verification of Interlaken FEC designs.
  • Easy to use command interface simplifies the test bench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.