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Verification IP

Hybrid Memory Cube
Verification IP

Faststream Technologies Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy-to-use and complete verification solution for SoC’s using the HMC Host Controller at the IP level or system-level. The HMC VIP consists of two components:

  1. HMC Device Model b. HMC Analyzer

The Device Model listens on the HMC interface (128-bit) for packets/flits and responds to requests from the Host. The device model VIP is designed to comply with the HMC Specification v 1.0 and supports all the transaction types mentioned in the specification.

The HMC Analyzer snoops both the TX and RX interfaces of the HMC Device/Host and captures all the packets/flits sent on the bus. It checks the links for compliance with the HMC specification, for example, Link retry, writes and reads. The Analyzer also includes coverage statistics to monitor the number and type of transactions on the HMC interface.

Both these components can be used in tandem or as stand-alone components in the Verification Environment.





  • HMC Device Model features
  • Fully compliant with the HMC Specification v1.0
  • 128-bit parallel interface for Transmit and Receive of packets/flits.
  • Supports Transaction layer initialization.
  • Supports the full set of commands specified by the HMC specification:
  • Mode Read
  • Mode Write
  • Write16/32/48/64/80/96/112/128
  • Posted Writes Write16/32/48/64/80/96/112/128
  • Read16/32/48/64/80/96/112/128
  • Error detection for CRC/Length/Sequence.
  • Error Injection at the HMC Device Model to test error detection and handling of the Host Controller.
  • Supports Link layer functions like Link Retry, Error Abort Mode.
  • Supports programmable settings for Link Failures and Link Retry.
  • Built-in support for Retry buffers and Link Input buffers.
  • Built-in support for Mode Registers needed to configure the Device Model.
  • Reports Error statistics and Error responses.
  • Generates responses to Reads/Write requests and Mode Read/Write requests, Retry requests.
  • HMC Analyzer Features:
  • Fully Compliant with HMC specification v1.0.
  • Two 128-bit parallel interfaces to snoop the HMC Transmit and Receive busses.
  • Monitors the HMC interfaces for transactions that take place on them.
  • Transmit and Receive interface monitoring independent of each other.
  • Performs CRC checks on the received packets/flits and flags errors when corrupted packets are detected.
  • Flags errors if packets/flits have malformed headers/tails.
  • Monitors and reports commands
  • Configurable parameters such as Verbosity levels, Threshold timers, retry error threshold limits and Coverage.
  • Supports three verbosity levels which change the amount of information printed in the logs.
  • Supports checking of Tag ID, Link ID and the Sequence number of packets.
  • Reports errors if Non-posted packet does not receive any response within a time frame or End of Simulation.
  • Transactions and Coverage reports displayed at the End of Simulation.
  • Performance statistics of the Device/Host such as Bandwidth/Speed are displayed.





  • Seamless integration with OVM/UVM Verification Environments.
  • Configurable components for easy creation of multiple instances of VIP.
  • Configuration options for easy controllability of the VIP.
  • Supports Directed, Random and Constrained Random testing.
  • Built-in Functional coverage to facilitate functional verification analysis.
  • Enables verification at IP-level, SoC, and System-level.
  • Documentation with Example codes for test benches and test cases.





  • SystemVerilog source code (encrypted).
  • Functional Coverage code which can be modified by users.
  • SystemVerilog testbench.
  • Sanity test cases which cover the functionality.
  • Sample Verification Environment

Block diagram: