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Just to introduce Faststream, we consider ourselves for Identifying and making a list of features to be validated as part of pre & post silicon validation.

As a part of Post-Silicon Validation we do work on  development of High level Test plan and get it reviewed by design engineers and developing the algorithms for various test flow design document and code.

Applying software validation techniques in PSV is the key to solving the puzzle. This can provide significant reduction in validation schedule while also improving and monitoring the coverage requirement.

We consider this as an art more than just a technology skill. At Faststream we combine our expertise in the whole gamut of silicon realization to provide our customers with a whole spectrum of silicon validation services. We always aim to reduce the schedule and cost for silicon validation while ensuring required functional coverage is achieved.


Following are typical phases that are performed as part of Post Silicon Validation:


  • Preparation of test plan and interacting with the designer to get more clarity on particular feature to be validated
  • Tracking and reviewing the features to be validated
  • Development of code in Embedded C, for all features to be validated
  • Participated in silicon bring up and executed tests on silicon with series of versions like, A0, A1, A2 and A3 etc.
  • Developed test cases for regression testing and stress testing
  • Filed JIRA tickets and tracked the issue till it get resolved
  • Took complete ownership of IPs that Faststream is  responsible
  • Troubleshooting hardware issues
  • Coordination with entire  Software Team of Faststream Technologies.
  • Debugging SOC issues with Oscilloscope.

Key Services

 Functional validation:


  • Core blocks – CPU, GPU, VPU, DMAC etc.
  • IO interfaces – USB, HDMI, SPI, I2C, CAN, Ethernet etc.
  • Subsystem-level functional validation exercising multiple core & IO interfaces.

 Power and Performance validation


  • Custom test cases & standard benchmarks.
  • Electrical validation across PVT conditions and wafer lots.
  • Power characterization of blocks, interfaces & voltage domains.
  • Power validation of subsystems under varying workloads.
  • Power validation of silicon under varying low-power states.


Board Bring up & Automation


  • Test case automation and regression.
  • Bare metal driver development for IO and core blocks & Board Bring-up.
  • OS-integrated functional, performance and power validation.
  • Data acquisition, analytics and reporting.

Our Experience Snapshot

 Tool Expertise


  • Measurement tools – CRO, LA, Spectrum Analyzer, Protocol Analyzer.
  • Automation tools / environments – Labview, PYTHON, PERL.
  • Emulators – Cadence Palladium, Mentor Veloce.
  • Debuggers – ARM DS5, Lauterbach.
  • IDEs – Keil, GNU, CCS.
  • RTL Simulators – Mentor Questa, Cadence NCSim, Synopsys VCS.

  Pre-Silicon Environments


  • Emulators (eg. Veloce, Palladium).
  • Off-the-shelf FPGA-based prototyping boards (eg. HAPS, Dini).
  • Custom-built FPGA-based prototyping boards.

 Post-Silicon Environments


  • Silicon evaluation boards – (with extra connectors, debugger-ports, test points, current.  measurement circuits)
  • Form-Factor ready Silicon evaluation boards.


As a part of Post Silicon Validation we have  executed following projects.


    •            Post Silicon Validation of UART IP
    •            Post Silicon Validation of TWI
    •            Post silicon validation of  USB 2.0


We have experience and knowledge in the following areas of PSV:


      • Board bring-up  
      • Characterization 
      • Signal Integrity   
      • Benchmarking   
      • System Level Testing (SLT)
      • Test content development   
      • Automation