ASIC Design Engineer (4+ Years) – Bangalore

Job Description

• Responsible for Front-End chip implementation including design integration, synthesis, and execution flow that starts with RTL coding and ends with the delivery of a netlist package ready for physical design.
• Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology, and timing constraint management.
• Work in collaboration with Physical Design Engineers in chip-level planning and integrations.
• Interact with verification engineers for test plan review, coverage debug.
• Technical mentoring for junior team members along with execution responsibilities.

Skills Required

• Strong Hands-on experience in Verilog/VHDL/System Verilog for design.
• Hands-on experience in Linting, Synthesis, Static Timing Analysis, and LEC.
• Should be able to work independently once the design requirements are specified.
• Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI.
• Knowledge of VP3, Perl is a plus.

Qualifications

• BE/B.Tech/M.Tech in Electronics and Communication Engineering/VLSI Design

Experience

• 4+ Years in ASIC Design